Japanese Unexamined Patent Application Publication No. 2006-278884 (PTL 1) discloses a method for mounting a semiconductor chip on a circuit board. Specifically, PTL 1 discloses a structure in which a frame-shaped spacer is disposed between a semiconductor chip and a circuit board. A plurality of bump electrodes are provided on a surface of the semiconductor chip so as to surround the center of the surface. The spacer is disposed below the hump electrodes. A plurality of connection electrodes that are connected to the bump electrodes are formed on an upper end surface of the spacer. A plurality of bump electrodes are formed on a lower end surface of the spacer, and these bump electrodes on the lower end surface of the spacer are joined to land electrodes formed on the circuit board.
Japanese Unexamined Patent Application Publication No. 6-232203 (PTL 2) discloses a mounting structure of a flip-chip large-scale integration (LSI), the mounting structure including an electronic circuit board and an LSI mounted on the electronic circuit board in a face-down manner. In PTL 2, a net-like spacer that is composed of an insulating material and that separates solder bumps adjacent to each other is disposed between the LSI and the electronic circuit board.